Shared buffer switching module

ABSTRACT

This invention relates to a switch module for use in an asynchronous transfer mode (ATM) system incorporating a shared buffer memory where incoming data cells are stored and subsequently transferred to exit ports. An incoming data cell is stored at a vacant buffer memory address on an interleaved, word-by-word basis and the address is placed in an appropriate priority queue in the appropriate exit port for the data cell. When time is available for transmission from the exit port, the data cell corresponding to the address at the head of the highest priority queue is sent to the exit port and transmitted.

RELATED APPLICATION

This patent application is a continuation-in-part of the followingapplication titled Channel Allocation Systems for Distributed DigitalSwitching Network, U.S Ser. No. 07/766,062, filed Sep. 26, 1991, nowabandoned.

This invention pertains to a buffered communication switch and, moreparticularly, to a buffered communication switch suitable for use in ATM(Asynchronous Transfer Mode) systems.

BACKGROUND OF THE INVENTION

In the early 1980's the CCITT (Consultative Committee on InternationalTelephone and Telegraph), working under the auspices of the UnitedNations and the International Telephone Communications Union, developedstandards for Narrow Band Integrated Services Digital Networks (N-ISDN)to allow limited capability for digital traffic in public networks. Inthe mid 1980's the CCITT study group began working on the communicationssuccessor referred to as the broadband ISDN (B-ISDN). The object of theB-ISDN was to eventually replace the entire public networkinfrastructure with a single communications fabric for all types ofcommunications traffic. In 1988 the CCITT decided to base the B-ISDNdevelopment on ATM (Asynchronous Transfer Mode). In June, 1992 the ATMForum was founded and it has since become the driving force in settingATM specifications. ATM network systems, because of their high speed andcapability of carrying all classes of communication traffic includingvoice, video and data, are commonly referred to as the communicationsuperhighway.

ATM standards require that data be sent in small cells of fixed length.The ATM cell contains fifty-three octets (bytes) of which the first fivebytes are a header (including a one-byte header check sum) and theremaining forty eight bytes are a data payload. ATM is aconnection-oriented technology where a cell is routed through one ormore intelligent switches each capable of interpreting the header andsending the cell onto a specific link headed toward its destination.Because of the relatively short cell length, cells from differentcommunications can be interleaved on the same communication link. Thismeans that ATM systems can handle time sensitive traffic, such as voiceor video, since the cells are not delayed at a switching node waitingfor completion of a long packet transmission as would be the case withprior packet switching technology.

Another advantage of the ATM approach is that the header includes datathat specifies the priority of the cell. Time sensitive traffic isnormally assigned a high priority. Computer data can be assigned apriority according to the customer's needs and willingness to pay. Thepriority can be used at each switching node to determine the order inwhich cells will be transmitted on the outgoing links.

In ATM systems, since there is often a need to delay a cell transmissionwaiting for higher priority traffic, an efficient buffering system isrequired at each switching node. Because of the high speed operation ofmost ATM systems, an efficient throughput can become essential.

One of the prior ATM switch designs incorporates a shared bus. Thisdesign uses cell buffering at the input port, and passes cells from aninput port to an output port over a shared bus. Some method ofarbitration is used to assign the shared bus capacity. Since congestionoccurs at the output ports, the arbitration must not allow an input portto pass a cell to an output port which is overloaded. Subsequent cellsare blocked at the input port and suffer unnecessary delay, unless amechanism is provided to bypass the blocking cell. The shared bus mustbe very high speed because it is shared by many high speed inputs.Buffer usage is relatively inefficient, because each port has a separatebuffer, and must provide worst case buffering. Multicast (from one tomany) is difficult to achieve on a shared bus.

Another prior switch design incorporates banyan networks which consistof networks of switch nodes having two input ports and two output ports.These use a prepended address code, which is used one bit at a time tomake a binary routing decision at each switch node. There are manyvariations, some of which require buffers at each node, as well asbuffers at the output port of the nodal network. Buffering at each nodeis particularly inefficient, since every node must consider a worst casecondition. Buffering at the output can allow a shared bufferpossibility, but such shared arrangements become complicated. Subsidiarymulticast networks are possible, but these further complicate theinternal buffering requirements.

Crossbar switches have also been proposed for ATM switching. A crossbarswitching structure is based on the provision of rectangular switcheswith buffering at each crosspoint. This is an implementation extensionof the nodal banyan switch, but is somewhat better because it is moreeasily extensible. Buffer usage is inefficient, however, and multicastis not easy to achieve.

A non-blocking space switch with output buffers has also been proposed.This requires the use of a non-blocking space switch (known as a ClosNetwork) to route between the input ports and the output ports, withbuffers on the output, either individual (inefficient) or shared.Multicast may require the further addition of buffers at the inputports. The shared buffers, if used, are complicated and look very muchlike a switch in their own right.

Another approach is to use shared memory switching in ATM systems. Cellsare transferred into and out of a shared memory on a cell-by-cell basis.The memory becomes both the buffering and the switching medium. Incomingcells are buffered in the shared memory, and are fetched from the memoryby the output ports. For multicast, the cell buffer is not reused untilall the necessary output ports have taken the cell. Memory usage isefficient, but the memory must be very high speed.

SUMMARY OF THE INVENTION

The system according to the invention is a switching moduleincorporating a shared memory buffer. When a cell is received, theheader is translated to determine the appropriate routing toward itsdestination and to determine cell priority. The cell is then stored at avacant address in a shared buffer memory and the address for the cell isplaced in a queue at the appropriate exit port. As soon as time isavailable for transmission on the outgoing link, the cell correspondingto the address at the front of the queue at the exit port is transmittedtoward its destination.

Each of the exit ports preferably includes several FIFO (First In FirstOut) registers to provide separate address queues for different cellpriority levels. As previously mentioned, the header of each incomingcell is translated to determine the appropriate exit port or ports andto determine the priority of the cell. The buffer memory address used tostore the cell is placed in the appropriate priority queue at the exitport or ports. The cells in the highest order priority queue aretransferred out of an exit port first, followed by cells in thesuccessively lower priority queues.

The system is preferably designed for a maximum data throughput into andout of the shared buffer memory. This is achieved according to oneaspect of the invention by transferring cells to and from the sharedbuffer on an interleaved word-by-word basis rather than a cell-by-cellbasis. The standard cell according to ATM standards includes fifty-threeoctets (bytes). One word from each incoming and outgoing cell istransferred between the ports and the shared buffer in succession. Thisinterleaved sequence is followed by another word from each of the cellsbeing transferred and so on. Transfer on an interleaved word-by-wordbasis increases the data throughput by eliminating delay in the celltransfer waiting for some of the slower operations, such as headertranslation.

The shared memory technique according to the invention facilitatesmulticasting (from one to many) which is within the ATM specificationsbut not easily achieved in most systems. This is easily accomplishedaccording to the invention by storing a cell address in more than oneexit port and not releasing the cell address until the cell has beentransmitted from each of the designated ports.

With the shared memory technique according to the invention it isnecessary to keep track of the shared memory addresses currently in useso that incoming cells can be assigned to unused addresses. Onetechnique according to the invention is to maintain a bit mapcorresponding to each of the address locations. When a new cell arrives,the bit map is searched using a high-speed content addressable techniqueand the first available unused address is assigned for storage of theincoming cell. When the cell transmission is complete, the bit map ischanged to indicate that the address is no longer in use. Anothertechnique is to maintain a linked list of vacant addresses. The addressat the head of the list is assigned to an incoming call and the headpointer is advanced to the next vacant address. After transmission ofthe cell from all of the designated exit ports is complete, the addressis added to the end of the linked list and the tail pointer for thelinked list is moved accordingly.

BRIEF DESCRIPTION OF THE DRAWINGS

Illustrative embodiments of the invention are set forth in the followingmore detailed specification. The specification includes the drawingswherein:

FIG. 1 is a block diagram of the overall switching module according tothe invention;

FIG. 2 is a timing diagram for the control sequence of the switchingmodule;

FIG. 3 is a schematic diagram of the switch module input port;

FIG. 4 is a schematic diagram of the switch module output port;

FIG. 5 is a schematic diagram of a content addressable bit-map buffermemory allocation system according to one embodiment of the invention;

FIG. 6 illustrates a linked list buffer memory allocation systemaccording to another embodiment of the invention; and

FIG. 7 is a schematic diagram of a translator for interpreting datacells.

OVERALL SWITCH MODULE LAYOUT

The overall layout for the switch module according to the invention isillustrated in FIG. 1 including a shared buffer memory 100 which is usedto store data cells while being transferred from an input port toselected output ports. According to a preferred embodiment, data istransferred to and retrieved from memory 100 via a 32-bit data bus 102and is addressed by means of a 13-bit address bus 104. A data cellaccording to ATM standards includes 53 octets (i.e. 53 8-bit bytes). Oneof these bytes is a header check sum which is removed at the input portafter being used to check the header. The data cell with the check sumremoved consists of 52 8-bit bytes and can be stored in the buffermemory as 13 32-bit words. To simplify addressing, a 16-word space isallocated for each data cell even though only 13 words are required. Adata cell address is defined by the 9 most significant bits of thememory address, the remaining 4 bits being used to identify the locationof the individual words making up the data cell.

The first input port 110 (referred to as input port zero) receives theincoming data cell in serial format via a cell receiver 112. One of theimportant functions of the cell receiver is to compare the header withthe check sum contained in the fifth byte of data cell. If the header isvalid, the check sum is removed and the remaining 52 bytes are passed onto a FIFO register 114. The FIFO register must be capable of storing atleast one complete data cell, and preferably as many as three datacells. The serial data cell is delineated and emerges as 52 8-bit bytes.The data cell passes from FIFO 114 through a switch input port 116 whereit is converted to a 32-bit word format. The data cell is thentransferred into buffer memory 110 via a data bus 102 to a locationdetermined by the address on address bus 104.

The first output port 120 (output port zero) is used to retrieve a datacell from a selected address via data bus 102. The data cell is receivedin a 32-bit word format by switch output port 126 and is passed on to aFIFO 124 in an 8-bit byte format. The data cell emerges from the FIFOand passes through a cell transmitter 122 which adds a header check sumas the fifth byte of the cell and transmits it in a serial format.

The first input port 110 and the first output port 120 are shown on theleft and right, respectively, for ease of illustration. In an actualsystem the first port would normally include both input port 110 andoutput port 120 so that bidirectional communications can be establishedvia a link connected to the port. The number of such ports in a switchmodule is a matter of engineering choice and depends largely on thedesired operating speed for the module. For the illustrative embodimenta switch module with sixteen ports was selected. The input ports eachsimilarly include a cell receiver 112, a FIFO 114 and a switch inputport 116, whereas the output ports each include a switch output port126, a FIFO 124 and a cell transmitter 122. The transceiver and celldelineation functions can be achieved using commercially availablechips. Transceivers operating at 155 Mb/s are available from TranSwitchas TXC-02301 and TXC-03003. Transceivers operating at 100 Mb/s areavailable from TranSwitch as AM7968 and AM7969. A suitable celldelineation block chip is available from TranSwitch as TXC 05150.

The data transfer within the switch module and the buffer addressing iscontrolled by a cell manager 130 which includes a buffer memoryallocation unit 132, a cell translator 134 and a sequencer 136. The cellmanager has access to data bus 102 and address bus 104. The cell manageris connected to activate a selected port via the port selection lines138. In addition, the cell manager supplies addresses to the switchports 116 and 126 as well as numerous control functions via connectionsnot shown in FIG. 1.

When a data cell is received at a switch input port, the header of thecell is transferred to translator 134 which determines the appropriateoutput port for the cell and the priority of the cell. The buffer memoryallocation 132 finds a vacant memory location and the incoming cell istransferred to that location on a word-by-word basis. The address isalso stored in a priority queue at the appropriate output port or ports.When the selected output port becomes available and the address is atthe head of the queue, the corresponding data cell is retrieved from thebuffer memory and transmitted from the selected port.

Shared buffer memory 100 can be of any size required by the switch. Forthe illustrative embodiment with sixteen input ports and sixteen outputports, a memory capable of storing 512 data cells was selected. Thesedata cells are addressed by the nine most significant bits on theaddress bus. A data cell is stored in a sixteen 32-bit word space. Amemory of 32K bytes is therefore selected for this illustrativeembodiment.

A control processor 150 is coupled to cell manager 130. The principaltask performed by the control processor is creating and deleting virtualpaths (VP) and virtual circuits (VC) between the associated switchmodules and other switches or interfaces in the network. The controlprocessor is capable of receiving its own program and data in data cellsfrom the network.

Activity Sequence

The sequence for the various activities in the operation of the switchmodule is controlled by sequencer 136 shown in FIG. 1. The sequencerincludes a ROM (read only memory) addressed by a clock and countercombination operating in a closed repetitive sequence. In the chosenembodiment, which has 16 ports, a 24-bit word is stored in the ROM foreach step in the sequence. The output bits from the ROM selectivelycontrol port selection, IN-translation read/write, OUT-translationread/write, buffer memory read/write, and cell release control. Therepetitive sequence is divided into 30 segments with each segment beingfurther subdivided into 16 sectors, one sector for each of the ports inthe switch module. The complete timing sequence includes 480 steps andtherefore 480 words are stored in the ROM.

The basic sequence of operations for an incoming data cell starts withtranslation of the header to determine the appropriate output port andthe cell priority. A vacant address is allocated in the buffer memoryand the incoming data cell is transferred to that address on aword-by-word basis. The storage of a word in memory using relativelyinexpensive, commercially available components requires about 18nanoseconds. The translation and memory allocation operations require onthe order of 90 nanoseconds. The translation operation therefore createsa bottleneck for the throughput of data through the switch. A similarbottleneck occurs during the transmission of a data cell since, becauseof possible multicasting, a further translation operation is used toinsure that the header is correct for each selected transmission link,

The activity sequence according to the invention transfers data to andfrom the buffer memory on a word-by-word basis arranged so that the datatransfers are not delayed by the slower translation and allocationfunctions. The activity sequence is illustrated in FIG. 2 including a30-sector primary sequence (to the left in the illustration) whereineach sector is subdivided into 16 segments with one segment for eachport. The starting points for the word-by-word transfers of data cellsfrom the different ports are distributed through the timing sequence sothat the slower translation and allocation operations can be carried outwhile data is being transferred to and from the shared memory withrespect to other ports.

The first line of the sector portion of the timing sequence in FIG. 2 isfor sector "0" which is primarily for "write" operations where words ofdata can be transferred to the shared buffer memory from each of theinput ports. The header translation operations for P0-IN (portzero--input translation), for P7-OUT (port seven--output translation),and P13-IN (port 13--input translation) are also initiated during sectorzero. The sequence for sector "0" is set forth in greater detail in thesegment/port activity portion of the illustration to the right in FIG.2.

In segment "0" (of sector "0") the first word of the data cell, whichincludes the header, is transferred to translator 134 (FIG. 1) and theIN-TRAN translation commences to determine the cell priority and theappropriate output port. The results from the translation are stored ina FIFO register within translator 134 when the translation is completed.In segment "1" the transfer of the data cell from port one is alreadyunderway and the 10th word of the data cell is transferred to the sharedbuffer memory. Similarly, during segments "2" to "6" the 6th, 2nd, 11th,7th, and 3rd words from ports 2 to 6, respectively, are transferred tothe shared memory. In segment "7" the header from the data cell inoutput port 7 is transferred to translator 134 and the results of theOUT-TRAN translation are stored in a second FIFO register whencompleted. In segments "8" to "12" the 8th, 4th, 12th, 9th, and 5thwords from ports 8 to 12, respectively, are transferred to the sharedmemory. In segment "13" the header from the data cell in input portthirteen is transferred to translator 134 and the results are stored ina third FIFO register within translator 134 when the IN-TRAN translationis completed. During segments "14" and "15" the 10th and 6th words aretransferred from ports fourteen and fifteen, respectively.

Sector "1" of the timing sequence is primarily for "read" operations,that is, retrieval of data cells from the shared memory by the outputports. In addition, the port 0 and port 13 data cell addresses aredistributed (P0-Addr and P13-Addr) and the revised header for theoutgoing link is received by port 7 (P7-Head). More specifically, duringsector 1, segment 0, the results of the port zero translation for theincoming cell are in the first FIFO register of translator 134 andbuffer memory allocation 132 indicates a vacant memory address. Duringthe IN-TRAN/Addr operation the vacant address is sent to the first inputport to control transfer of the data cell to the memory and is also sentto the appropriate output port together with the priority indication forthe cell. During segments "1" to "3", the 12th, 8th and 4th words of therespective data cells are delivered to output ports 1 to 3. Next, duringsegment "4", the header is transferred to output port 4. During segments"5" and "6", the 9th and 5th words are delivered to their respectiveoutput ports. During segment "7" the OUT-TRAN/Header operation takesplace where the modified header is transferred to output port 7. Duringsegments "8" to "12", the 10th, 6th, 3rd, 11th and 7th words aretransferred respectively to output ports 8 to 12. During segment "13" avacant memory address is transferred to input port 13 and to theselected outpost port. During segments "14" and "15" the 12th and 8thwords are transferred to respective output ports 14 and 15.

It is important to note that the translator operations IN-TRAN andOUT-TRAN are each separated by five or more segments. This separationpermits the slow translator operations to be carried out while thefaster word transfer operations go forward.

The translator operations are distributed more or less evenly throughoutthe activity sequence. The read and write operations for the words ofthe data cell come in sequence after completion of the respectivetranslation operations.

The port activity sequence, as seen from port zero, is extracted fromFIG. 2 and is set forth in the following table:

    ______________________________________                                        PORT ZERO ACTIVITY SEQUENCE                                                   Sector                                                                              Action  Data                 Port Cell                                  ______________________________________                                        0     Write   Incoming Header (IN-TRAN)                                                                          IN   N                                     1     Read    Buffer Address (result of IN-                                                                      IN   N                                                   TRAN/Addr)                                                      2     Write   Incoming header to buffer                                                                          IN   N                                     3     Read    Data word 4 from buffer                                                                            OUT  M-1                                   4     Write   Data word 1 to buffer                                                                              IN   N                                     5     Read    Data word 5 from buffer                                                                            OUT  M-1                                   6     Write   Data word 2 to buffer                                                                              IN   N                                     7     Read    Data word 6 from buffer                                                                            OUT  M-1                                   8     Write   Data word 3 to buffer                                                                              IN   N                                     9     Read    Data word 7 from buffer                                                                            OUT  M-1                                   10    Write   Data word 4 to buffer                                                                              IN   N                                     11    Read    Data word 8 from buffer                                                                            OUT  M-1                                   12    Write   Data word 5 to buffer                                                                              IN   N                                     13    Read    Data word 9 from buffer                                                                            OUT  M-1                                   14    Write   Data word 6 to buffer                                                                              IN   N                                     15    Read    Data word 10 from buffer                                                                           OUT  M-1                                   16    Write   Data word 7 to buffer                                                                              IN   N                                     17    Read    Data word 11 from buffer                                                                           OUT  M-1                                   18    Write   Data word 8 to buffer                                                                              IN   N                                     19    Read    Data word 12 from buffer                                                                           OUT  M-1                                   20    Write   Data word 9 to buffer                                                                              IN   N                                     21    Read    Old outgoing header from buffer                                                                    OUT  M                                     22    Write   Old outgoing header for                                                                            OUT  M                                                   OUT-TRAN                                                        23    Read    New outgoing header for                                                                            OUT  M                                                   OUT-TRAN                                                        24    Write   Data word 10 to buffer                                                                             IN   N                                     25    Read    Data word 1 from buffer                                                                            OUT  M                                     26    Write   Data word 11 to buffer                                                                             IN   N                                     27    Read    Data word 2 to buffer                                                                              OUT  M                                     28    Write   Data word 12 to buffer                                                                             IN   N                                     29    Read    Data word 3 to buffer                                                                              OUT  M                                     ______________________________________                                    

For an incoming data cell at port zero, the translation is performedduring sector "0" and the vacant address for the incoming data cell issupplied to the ports in sector "1". The header is written into thebuffer memory in sector "2" and the following twelve words of theincoming data cell are written into memory in sectors "4", "6", "8",etc.

For an outgoing data cell at port zero the sequence begins at sector"21" where the original header of the data cell is transferred to portzero and in sector "22" where the header is transferred to thetranslator. The results of the translation are returned to output portzero as a new header in sector "23". Data words 1, 2, and 3 aretransferred to output port zero in sectors "25", "27" and "29".

Data word 4 is transferred to output port zero in sector "3" and datawords 5 to 12 are transferred in sectors "5", "7", "9", "11", "13","15", "17", and "19".

The Switch Module Input Port

Switch module input port 116, described in FIG. 1, is shownschematically in FIG. 3. An incoming data cell including fifty-threeoctets (bytes) passes through the cell receiver 112 where the header iscompared with the check sum in the cells. If the data cell is valid, thecheck sum is removed and the remaining fifty-two bytes are passed on toone or more FIFO's 114. The data cell is organized into 52 eight-bitbytes in FIFO 114. The data cell is transferred out of the FIFO in 9-bitwords each including an 8-bit data byte and a 9th bit which is a "1"only if it accompanies the last byte of a data cell.

The data cell is reorganized into 32-bit words in the switch moduleinput port. A vacant buffer memory address is assigned by buffer memoryallocation unit 132. The data cell is then transferred to shared buffermemory 100 on a word-by-word basis under the control of sequencer 136.

The transfer of the data cell from FIFO 114 to data bus 102 isaccomplished by registers 302-305. Shift register 302 is athirty-three-bit arrangement designed to receive 9-bit words from FIFO114 via a 9-bit bus 340. Each 9-bit word includes an 8-bit byte of dataplus a 9th bit which is "0" unless the word is the last word of a datacell. The transfer from FIFO 114 to register 302 is controlled by aclock 332 which is part of cell receiver 112. When four data bytes havebeen transferred into register 302 and successively moved up in theregister, register 302 is full including 32 data bits and a locator bitin the 33rd bit location 312. The 32-bit data word plus locator bit istransferred into a 12×33 FIFO register 303. The transfer into FIFO 303is achieved by dividing clock 232 by four in a divider 334. Divider 334provides a shift pulse for every 4 data bytes from FIFO 114. The 33rdbit is used for the locator bit which indicates the end of the data cellas it passes through FIFO 303. Registers 304 and 305 are each 33-bitregisters for transfer of the 32-bit words. These registers include bits314 and 315 respectively, to provide cell location. Register 305 iscapable of receiving data from register 304 as well as from data bus102. Register 305 is also capable of transferring data to shared buffermemory 100 via data bus 102.

An address unit 320 is used to provide data addresses via bus 104 forlocating transferred data in the shared buffer memory. The address unitincludes a 9-bit register 324 which receives data cell addresses frombuffer memory allocation unit 132. The address unit also includes a4-bit counter 322 which provides the least significant bits of a memoryaddress. To simplify addressing each data cell has a space allocation ofsixteen 32-bit words, even though a 13-word space would be adequate fora data cell. This is done to simplify the addressing since, with thearrangement in the illustrative embodiment, each of the 9-bit words inregister 324 is capable of defining a data cell space in memory. Thus,the 9-bit register 324 can uniquely identify 512 data cell spaces in theshared memory, whereas counter 322 provides an additional 4 bits whichdefine the individual word locations of the data cells. In operation,when a data cell is to be transferred, a 9-bit address is transferredinto register 324 and counter 322 is initially set to zero so that itpoints to the start of the space allocated for the data cell. Counter322 is advanced each time a data word is transferred to the memory sothat address unit 320 always points to the address for the next word tobe transferred from the input port to buffer memory 100.

A read clock 336 is controlled by sequencer 136 and a port input controlunit 330 (through connections not shown). The read clock controls thetransfer of data out of the FIFO register 303 and registers 304, and 305into the buffer memory. The port input control 330 receives signals fromthe locator bits 312-315 in the registers 302-305. Locator bits 312-315indicate the location of the end of the data cell being passed throughthe registers. Control unit 330 also receives an indication as to whenFIFO 114 in the cell receiver is full and ready to transfer a data cell.The port input control 330 further controls the in-clock for transfer ofthe data into the registers 302 and 303 as well as read clock 336 whichcontrols the transfer of the data cell from registers 303-305 intoshared memory 100.

The operation of the switch module input port in FIG. 3 starts with adata cell being received by the cell receiver which compares the checksum with the header to determine if a valid data cell has been received.If so, the check sum is removed and the remaining 52 bytes of the datacell are transferred into a FIFO 114. When the registers in the switchmodule input port are empty, a data cell is transferred from FIFO 114into registers 302 and 303. In the transfer through register 302 the8-bit bytes are converted into 32-bit words.

The transfer of the data cell into the shared memory commences bystepping the data cell into registers 304 and 305 so that the cellheader is located in register 305. The header is transferred totranslator 134 in the cell manager which examines the header anddetermines the appropriate output port and priority status of the datacell. The designated output port and priority status are stored in oneof the output FIFOs, such as 140. Buffer memory allocation unit 132provides a vacant memory address to address register 324.

The transfer of the data cell to the vacant address in buffer memory 100on a word-by-word basis is controlled by sequencer 136. The data cell isstepped to the right toward register 305 each time a word is transferredto the buffer memory via the data bus. Each transfer also advances theaddress counter 322 by one step so that the address unit 320 alwayspoints to the next word address. Each transfer of a data word to theshared memory via data bus 102 is to the address to which the addressunit 320 points via address bus 104.

The switch module input port must also include the capability ofhandling special meta signaling cells. Certain virtual paths and virtualcircuits are set aside for signaling purposes. For example, a terminalstation may request virtual path/virtual circuit information forreaching a certain destination. When such a meta cell is detected in thetranslator, the translation must provide a new header in addition toassigning a buffer space and selecting an outgoing port. The outgoingport will connect to the control processor 150, and the new header willdistinguish which incoming port received the meta cell. Other trafficmanagement cells may be received and detected by the translator. Thesecells require traffic information to be returned to the sender, so therequested information is inserted into the data section of the cellwhich is then returned to the originating terminal via the output portfor the same link with an appropriately modified header.

The switch module input port must also be capable of receiving datacells which are addressed to control processor 150 associated with theswitch module.

Switch Module Output Port

The switch module output port 120 retrieves data cells from sharedmemory 100 according to the addresses at the head of a priority queue.

The number of priority classifications is a matter of design, but afour-level priority appears to be adequate for most purposes and is usedin the illustrative embodiment. The switch module output port, asillustrated in FIG. 4, includes four separate priority queues, i.e.FIFOs 450-453. The FIFOs are each 10 bits wide in order to accept a9-bit data cell address plus an additional bit for indicatingcongestion. The length of the FIFO is a matter of design depending onthe anticipated needs. The capacity to store 16 addresses at eachpriority level should be adequate for most purposes and is used in theillustrative embodiment.

When a data cell is received via the: switch module input port, theheader is transferred to cell translator 134 which determines theappropriate output port and the cell priority. Buffer memory allocationunit 132 provides a vacant address for storing the incoming data cell.This address is sent to the selected output port via bus 455 and thepriority information is provided to the priority assignment logic 460.The priority assignment logic directs the incoming address to thepriority FIFO 450-453 corresponding to the priority status. Each of thepriority FIFOs are arranged to detect congested conditions when morethan 12 addresses are in the priority queue. Any such congestion isindicated in the 10th bit associated with a 9-bit address.

The switch module output port includes an address unit 440 similar tothe address unit in the switch module input port. The address unitincludes a 9-bit register 444 for the data cell address and a 4-bitcounter 442 which points to the word address within the data cell. Anext address select unit 462 selects the address at the head of thehighest priority queue and transfers that address to register 444 when adata cell is to be transmitted.

Registers 410-413 are used to receive the data cells from memory 100 viadata bus 102 in a 32-bit word format. Register 410 can receive a dataword from the data bus or can supply a data word to the data bus. When adata cell is being transmitted, the first word, which is the header, isfirst transferred to register 410 from memory 100. The header is thentransferred from register 410 to translator 134 via the data bus andsubsequently modified and returned to register 410. The data cell isthen stepped into registers 410-412 word at a time under control of awrite clock 436 through interconnections not shown in FIG. 4.

The transfer of a data cell to cell transmitter 122 via register 413 iscontrolled by an out clock 432 in the cell transmitter. The out clockcontrols the transfer of the data cell in 8-bit bytes from register 413into 52×8 FIFO register 124. Out clock 432 divided by four in divider433 also controls the transfer of the data cell in 32-bit words fromFIFO register 412. Thus, a 32-bit word is transferred into register 413and shifted downward and transferred into FIFO 124 as 8-bit bytes.

The 33rd bit 420-423 of registers 410-413, respectively, is used for alocator bit which is a "1" for the last word of the data cell. Thelocator bit is inserted into the 33rd bit of register 410 by a portoutput port control 438. The port output control is connected to monitorthe locator bit as the data cell is stepped through registers 410-413.The locator bit 423 is also connected to FIFO 124 in the celltransmitter to signal the end of a cell being transferred to the FIFOregister.

In operation the switch module output port retrieves data cells from theshared memory according to the address at the head of the priority queuefor the port. When a data cell is received via an input port (FIG. 3),the header of the data cell is sent to cell translator 134 in the cellmanager. The translator determines the appropriate output port for thecell and the priority of the cell. The buffer memory allocation unit 132determines a vacant address for storing the data cell in shared memory100. The address is sent to the output port via bus 455 (FIG. 4) and thepriority indication is sent to priority assignment logic 460. Thepriority assignment logic decodes the priority indication and gates theaddress into the appropriate one of the priority queue registers450-453. If the priority register has more than a predetermined numberof addresses already in the queue, priority assignment logic 460 adds acongestion indication to the 10th bit associated with the address.

The output port retrieves data cells according to the addresses at thehead of the highest order priority queue. More specifically, nextaddress select unit 462 first retrieves data cells according to theaddresses in the highest order priority queue 450, then retrieves datacells according to the addresses in the next highest priority queue 451followed by retrieval according to addresses in the third priority queue452 and, finally, retrieves data cells according to the addresses in theremaining priority queue, 453. The addresses from the priority queuesare transferred to the 9-bit address register 444 via bus 456. The 9-bitaddress points to the starting point in the shared memory for the datacell. Counter 452, which provides the four least significant bits of thememory address, is set to zero. Accordingly, the 13-bit address suppliedto the memory via address bus 104 points to the word at the beginning ofthe data cell in the memory.

Under control of sequencer 136 and port output control 438, the datacell at the designated address is transferred from memory 100 to celltransmitter 122. The data cell as retrieved from memory is in a 32-bitformat. The data words are transferred a word at a time to register 410via bus 102 and stepped into registers 411 and 412 as additional wordsarrive. The complete data cell occupies registers 410, 411 and 412. Thefirst word, which is the 4-byte header for the cell, is transferred tothe cell translator 134 for an update of the virtual path and virtualcircuit in the header according to the link through which the data cellis to be transmitted. Such updating of the header is required in amulticasting situation where the same cell is being transmitted toseveral different destinations. The updated header is transferred fromthe translator into register 410 via data bus 102. The subsequent wordsof the data cell are then shifted into registers 410-412. When the lastword of a data cell is received, a locator bit is inserted in the33rd-bit location of register 410 to indicate the end of the data cell.The location of the data cell, as it is stepped through the register, isdetermined by monitoring the 33rd-bits in segments 421-423.

Register 413, under the control of out clock 432 and divide-by-fourdivider unit 433 converts the 32-bit words of the data cell into 8-bitbytes for transfer into FIFO 124. After the data cell has beentransferred to FIFO 124 in the cell transmitter, a check sum for theheader is added as the fifth byte and the data cell is then transferredto the output link in a serial form.

Buffer Memory Allocation--Content Addressable Memory Embodiment

Buffer memory allocation could theoretically be achieved by maintaininga bit map of all the assigned addresses and port assignments. Because ofthe multicasting possibility, the bit map must keep track of assignedaddresses and each port from which the data cell at the address is to betransmitted. The bit map must be updated each time a data cell istransmitted and the buffer memory address must be indicated as free whenall the intended data cell transmissions from a particular address havebeen completed. Such a memory allocation unit could be constructed usinga 512×16 memory array and a search routine which would continue until avacant address is found. Such a straight forward approach, however,would be unsatisfactory for many applications because of the largevariation in the number of searches that may be required to find a freeaddress and because of the time which may be required for the worst casesearch.

One of the preferred buffer memory allocation unit embodiments accordingto the invention is illustrated in FIG. 5 using a 512×16 bit RAM bufferusage memory 520 in combination 512-bit array content addressable memory(CAM) 510. The buffer usage memory is organized so that the portassignments for a data cell are reflected in the 16-bit word associatedwith the address assignment for the data cell. Each time an address isassigned for an incoming data cell, a logic block 522 associated withmemory 520 places a "1" bit in each memory location corresponding to theport address assignment. Each time a data cell is transmitted, theaddress and port information for the transmitted data cell is sent tologic block 522 to erase the corresponding memory bit in usage memory520. In this manner the usage memory maintains a current map indicatingthe addresses in use and the ports through which data cells are to betransmitted. Content addressable memory 510 includes a 512-bit memoryarray, i.e. one bit for each of the 512 assignable addresses in sharedbuffer memory 100. The bits in the CAM are automatically updated frombuffer usage memory 520 via logic block 522 so that an address bit inthe CAM becomes "0" when a data cell has been transmitted from all theassigned ports. Content addressable memory 510 can be organized into anyconvenient bit array such as one including 512 bits arranged into 16rows and 32 columns. The memory bits in the CAM are interconnected sothat the memory can be searched row at a time or column at a timethrough the associated CAM control and address unit 516. In searchingfor a free buffer memory address the Cam control and address unitsearches all the rows in parallel at one time to locate the rowsincluding one or more "0"s indicating free addresses using flow-throughlogic. The search then continues by examining the bits in a selected rowto locate a free address.

The search result is a 9-bit address which is free in shared buffermemory 100. This address is transferred from the CAM to a FIFO register530. Preferably, FIFO 530 is capable of storing two addresses since therequest for a second free address can be received before the firstaddress is utilized. The end address unit 532 functions as a latch forreleasing the buffer usage bits. A content addressable memory withcharacteristics similar to those described in the above-identifiedpatent application Ser. No. 07/766,062 can be used.

Buffer Memory Allocation-Linked List Embodiment

An alternative technique for assigning buffer memory addresses toincoming cells is through a linked list as illustrated in FIG. 6. Thelinked list is set up in a memory associated with a microprocessor.Preferably, the microprocessor is dedicated to the task of achieving arapid address assignments as new cells arrive. Basically, the techniqueinvolves maintaining a linked list of the currently unassigned buffermemory addresses. When a buffer memory address is assigned to anincoming cell, the address is removed from the linked list. When abuffer memory address is released meaning that the data cell has beentransmitted from all the assigned ports, the address is added to the endof the linked list. In this fashion, the system always maintains acurrent list of the unassigned buffer addresses available for assignmentto incoming cells.

The memory for the linked list is set up as illustrated in FIG. 6. Allof the potentially available 512 memory addresses (in 9-bit form) aremaintained on a permanent list, 610-615. Each buffer address has anassigned pointer 620-625 and a 16-bit space for port assignments630-635. A head pointer 640 points to the head of the linked list, and atail pointer 642 points to the end of the linked list. Initially, beforeany buffer addresses are assigned, the head pointer points to the firstbuffer address 610. The pointers associated with the buffer addresseseach point to the next buffer address, e.g. pointer 620 points to bufferaddress 611, pointer 621 points to buffer address 612, etc. The tailpointer 642 points to the last buffer address 615. When a request for abuffer memory address is received, the buffer address pointed to by headpointer 640 is assigned to the incoming cell. The pointer 620 associatedwith the assigned buffer memory address is transferred to the headpointer, thereby removing the first buffer memory address from thelinked list. When the next request for a buffer memory address isreceived, the head pointer is pointing to the next buffer address 611,which is assigned, and the associated pointer, 621, is transferred tothe head pointer. Thus, each time a request for a buffer address isreceived, the address at the head of the list is assigned and the headpointer is advanced so that it points to the next address on the linkedlist of unused addresses.

When a buffer address is released and available for reassignment, it isadded to the end of the linked list. Each time a data cell istransmitted from an output port, the port assignment bit is changed to"0" and the 16-bit port assignment is checked to determine if any "1"sremain. If not, the address is released. The pointer to the newlyreleased address is inserted as the pointer associated with the lastbuffer memory address then on the list as pointed to by tail pointer642. The tail pointer is then reset so that it points to the newly addedbuffer address at the end of the list. In this manner the newly releasedbuffer memory address is added to the end of the linked list.

The initial linked list, as illustrated in FIG. 6, shows an orderly listprogressing from top to bottom. In time the list will be modified sothat the order appears to jump around in random fashion. The lack oforder in the list, however, has no significant adverse effect on theoperation of the linked list buffer addressing scheme.

Translator

The function of translator 134 is to receive the 32-bit header of a datacell to perform an IN-TRAN translation to determine the appropriate exitport and the cell priority or an OUT-TRAN translation to determine thevirtual path and virtual circuit for the outgoing data cell which is tobe transmitted. The OUT-TRAN translation becomes necessary formulticasting where the same cell is sent to several destinations eachhaving a different virtual path/virtual circuit. The ATM standardsprovide bits in the header for a range of 4k virtual path ("VP")addresses, and 64k virtual circuit ("VC") addresses for each virtualpath. In the illustrative embodiment there are sixteen ports, each ofwhich could potentially have the full range VP/VC addresses and requireon the order of 2³² translations. Since this is far more than areeconomically useable in the foreseeable future, a data compression isdesirable in the translator.

The design of the data compressor depends on the number of VP/VCcombinations the system is intended to service. An example of datacompression for the translator in accordance with the invention isachieved as illustrated in FIG. 7. Translator 134 is located within thecell manager and responds to 12 bits for the virtual path designation,16 bits for the virtual circuit designation, and 4 bits for the portdesignation. The cell manager extracts the 28-bit VP/VC designation fromthe data on the data bus and adds the 4-bit port designation accordingto the active port.

In the example in FIG. 7, the incoming 32 bits are divided into two 16bit groups 603 and 605 which are supplied respectively to 64k×8 RAMs 602and 604. The 8 bits 606 from memory 602 and the 8 bits 607 from memory604 are supplied as a 16-bit address to a 64k×64 memory translationtable 608. The translation emerges from memory 608 as a 64-bit wordwhich includes 32 bits for the incoming IN-TRAN cell translation 620 and32 bits for the outgoing OUT-TRAN translation 622. The IN-TRANtranslation for an incoming data cell supplies the outgoing port andpriority for the cell. The OUT-TRAN translation for an outgoing datacell supplies the virtual path and virtual circuit appropriate for theoutgoing link. The 64-bit word emerging from memory 608 is more thanadequate for the translations and, hence, some spare bits are availablefor other purposes. The translation result is placed in a selected oneof three 64-bit FIFO registers 610.

The allocation of the VP/VC and port bits to address RAMs 602 and 604 isa matter of design choice depending largely upon the expecteddistribution of the virtual paths and virtual circuits. The contents ofthe 64k locations of the translation table are set by control processor150 shown in FIGS. 1 and 3. The control processor creates and deletesthe VP/VC addresses used in the translation table. Usually the VP/VCaddress information is maintained in the translation table only for theduration of a call.

Although only a few illustrative embodiments have been described indetail in the foregoing specification, it should be obvious that thereare numerous variations in the circuit configurations and operatingsequences which are within the contemplated scope of the invention. Theinvention is more particularly defined in the appended claims.

I claim:
 1. A buffered communication switch for switching data cellsbetween input ports and selected output ports, comprising:one or moreinput ports for receiving incoming data cells; a plurality of outputports; a shared buffer memory for storing data cells received via saidone or more input ports while awaiting transmission via one or more ofsaid output ports; a common bus interconnecting said input ports, saidoutput ports, and said shared buffer memory; means for examining saidincoming data cells to select one or more of said output portsappropriate for transmission of the cell; means for selecting a vacantaddress in said shared buffer memory for storing one of said incomingdata cells; means for storing said one of said incoming data cells toprovide a stored data cell at said vacant address and for storing theaddress thereof at one or more of said output ports selected fortransmission of said stored data cell; means for retrieving said storeddata cell when time is available for transmission thereof via saidselected one or more output ports; and wherein the transfer of anincoming data cell from said input ports to said shared buffer memory isinterleaved via said common bus with the transfer of data cells fromsaid shared buffer memory to said output ports.
 2. A bufferedcommunication switch according to claim 1 wherein said means forselecting a vacant address includesmeans for maintaining a linked listof vacant addresses; means, coupled to said means for storage, forremoving an address from said linked list when assigned for storage of adata cell; and means, coupled to said means for retrieving, for addingan address to said linked list when the data cell stored at the addresshas been transmitted from all selected ports for said data cell.
 3. Abuffered communication switch according to claim 1 wherein said meansfor selecting a vacant address includesa memory map maintained toindicate currently assigned exit ports for stored data cells; and acontent addressable memory means using parallel flow through logic todetermine a vacant address and for storing said incoming data cell atsaid vacant address in said shared buffer memory.
 4. A bufferedcommunication switch according to claim 1 wherein said means forexamining incoming data cells includes a translator for examining theheader of said incoming data cell to determine the output port or portsand the cell priority.
 5. A buffered communication switch according toclaim 4 for routing data cells according to virtual path and circuitdesignations in the data cell wherein said translator operates on a datacompressed format according to the number of virtual paths and circuitsbeing serviced.
 6. A buffered communication switch according to claim 1wherein said means for examining incoming data cells includes atranslator for examining and translating the header of said incomingdata cell and wherein other data cells are being transferred to and fromsaid shared memory on a word-by-word basis while translations are beingcarried out.
 7. A buffered communication switch according to claim 6further includingmeans for transmitting said data cell from one or moreof said output ports when time is available; and translator means forexamining the header of each outgoing data cell and changing said headeraccording to the outgoing transmission link.
 8. A buffered communicationswitch according to claim 1 wherein said means for storing and saidmeans for retrieving operate on a word-by-word interleaved basis.
 9. Abuffered communication switch for the priority switching of data cellsbetween input ports and selected output ports, said data cells eachhaving a data cell priority, comprising:one or more input ports forreceiving incoming data cells; a plurality of output ports eachincluding a plurality of priority address queues associated therewith; ashared buffer memory for storing said incoming data cells received viasaid one or more input ports while awaiting transmission via one or moreof said output ports; a translator for examining said incoming datacellsto determine the data cell priority, and to select one or more ofsaid output ports for subsequent transmission of said incoming datacells; an address selector for selecting a vacant address in said sharedbuffer memory for storing an incoming data cell; means for storing saidincoming data cell to provide a stored data cell at said vacant addressdetermined by said address selector and for storing said vacant addressin a selected priority queue at said one or more output ports selectedby said translator for subsequent transmission of said stored data cell;and means for retrieving coupled to said shared memory to receive saidstored data cell at said address in said shared memory for transmissionof said stored data cell via said selected output port when said addressis at the head of the highest occupied priority queue at said selectedport.
 10. A buffered communication switch according to claim 9 whereinsaid address selector for selecting a vacant address includesmeans formaintaining a linked list of vacant addresses; means, coupled to saidmeans for storage, for removing an address from said linked list whenassigned for storage of a data cell; and means, coupled to said meansfor retrieving, for adding an address to said linked list when the datacell stored at the address has been transmitted from all selected portsfor said data cell.
 11. A buffered communication switch according toclaim 9 wherein said address selector for selecting a vacant addressincludesa memory map maintained to indicate currently assigned outputports for stored data cells; and a content addressable memory meansusing parallel flow through logic to determine a vacant address and forstoring said incoming data cell at said vacant address in said sharedbuffer memory.
 12. A buffered communication switch according to claim 9for routing data cells according to virtual path and circuitdesignations in the data cell wherein said translator operates on a datacompressed format according to the number of virtual paths and circuitsbeing serviced.
 13. A buffered communication switch according to claim 9wherein said translator examines and translates the header of saidincoming data cell and wherein other data cells are being transferred toand from said shared memory on a word-by-word basis while translationsare being carried out.
 14. A buffered communication switch according toclaim 13 further includingmeans for transmitting said data cell from oneor more of said output ports when time is available; and furthertranslator means for examining the header of each outgoing data cell andchanging said header according to the outgoing transmission link.
 15. Abuffered communication switch according to claim 9 wherein said meansfor storing and said means for retrieving operate on a word-by-wordinterleaved basis.
 16. A buffered communication switch for switchingmulti-word data cells between input ports and selected output ports,comprising:a plurality of input ports for receiving incoming data cells;a plurality of output ports; a shared buffer memory for storing saidincoming data cells received via said input ports while awaitingtransmission via one or more of said output ports; a translator forexamining said incoming data cells to designate one or more of saidoutput ports for transmission of said incoming data cells; an addressselector for selecting a vacant address in said shared buffer memory forstoring an incoming data cell; means for storing said incoming data cellat said vacant address to provide a stored data cell and for storing theaddress thereof at said one or more output ports selected fortransmission of said stored data cell; and means for retrieving coupledto said shared memory to receive said stored data cell at said addressin said shared memory when time is available for transmission of saiddata cell via said selected one or more output ports; said means forstoring and said means for retrieving being operable to transfer datacells to and from said shared buffer memory on a word-by-word basis. 17.A buffered communication switch according to claim 16 wherein saidaddress selector includesmeans for maintaining a linked list of vacantaddresses; means, coupled to said means for storage, for removing anaddress from said linked list when assigned for storage of a data cell;and means, coupled to said means for retrieving for adding an address tosaid linked list when the data cell stored at the address has beentransmitted from all selected ports for said data cell.
 18. A bufferedcommunication switch: according to claim 16 wherein said addressselector includesa memory map maintained to indicate currently assignedoutput ports for stored data cells; and a content addressable memorymeans using parallel flow through logic to determine a vacant addressfor storing said incoming data cell at said vacant address in saidshared buffer memory.
 19. A buffered communication switch according toclaim 16 wherein said translator for examining incoming data cells alsodetermines cell priority.
 20. A buffered communication switch accordingto claim 19 for routing data cells according to virtual path and circuitdesignations in the data cell wherein said translator operates on a datacompressed format according to the number of virtual paths and circuitsbeing serviced.
 21. A buffered communication switch according to claim16 wherein said translator examines and translates the header of saidincoming data cell and wherein other data cells are being transfered toand from said shared memory on a word-by-word basis while translationsare being carried out.
 22. A buffered communication switch according toclaim 21 further includingmeans for transmitting said data cell from oneor more of said output ports when time is available; and furthertranslator means for examining the header of each outgoing data cell andchanging said header according to outgoing transmission link.
 23. Abuffered communication switch for the priority switching of multiworddata cells between input ports and selected output ports, said datacells each having a data cell priority, comprising:one or more inputports for receiving incoming data cells; a plurality of output portseach including a plurality of priority address queues associatedtherewith; a shared buffer memory for storing said incoming data cellsreceived via said one or more input ports while awaiting transmissionvia one or more of said output ports; a translator for examining saidincoming data cellsto determine the data cell priority, and to selectone or more of said output ports for subsequent transmission of saidincoming data cell; an address selector for selecting a vacant addressin said shared buffer memory for storing an incoming data cell; meansfor storing said incoming data cell to provide a stored data cell atsaid vacant address and for storing the address thereof in a selectedpriority queue at each of said one or more output ports selectedaccording to said cell priority; and means for retrieving coupled tosaid shared buffer memory to receive said stored data cell at aretrieval address in said shared memory when said retrieval address isat the head of the highest occupied priority queue at said selectedport; said means for storing and said means for retrieving beingoperable to transfer data cells to and from said shared buffer memory onan interleaved word-by-word basis.
 24. A buffered communication switchaccording to claim 23 wherein said address selector includesmeans formaintaining a linked list of vacant addresses; means, coupled to saidmeans for storage, for removing an address from said linked list whenassigned for storage of a data cell; and means, coupled to said meansfor retrieving, for adding an address to said linked list when the datacell stored at the address has been transmitted from all selected portsfor said data cell.
 25. A buffered communication switch according toclaim 23 wherein said address selector includesa memory map maintainedto indicate currently assigned exit ports for stored data cells; and acontent addressable memory means using parallel flow through logic todetermine a vacant address and for storing said incoming data cell atsaid vacant address in said shared buffer memory.
 26. A bufferedcommunication switch according to claim 23 for routing data cellsaccording to virtual path and circuit designations in the data cellwherein said translator operates on a data compressed format accordingto the number of virtual paths and circuits being serviced.
 27. Abuffered communication switch according to claim 23 wherein saidtranslator examines and translates the header of an incoming data cellwhile other data cells are being transferred to and from said sharedmemory on an interleaved word-by-word basis.
 28. A bufferedcommunication switch according to claim 23 further includingmeans fortransmitting said data cell from one or more of said output ports whentime is available; and further translator means for examining the headerof each outgoing data cell and changing said header according tooutgoing transmission link.
 29. A method of telecommunication switchingof multi-word data cells between input ports and selected output ports,comprising the steps of:receiving an incoming data cell via an inputport; examining said incoming data cell to select one or more outputports appropriate for retransmission of the cell; using a shared buffermemory for storing incoming data cells received via the input portswhile awaiting transmission via one or more of the output ports;selecting a vacant address in the shared buffer memory for storing saidincoming data cell; storing said incoming data cell at said vacantaddress to provide a stored data cell; storing said address at one ormore output ports selected for re-transmission of said stored data cell;and retrieving said stored data cell in the shared memory when time isavailable for re-transmission of said stored data cell via each of saidone or more selected output ports; and wherein the transfer of incomingdata cells for storage in said shared buffer memory is interleaved withthe transfer of stored data cells from said shared buffer memory to saidoutput ports.
 30. The method according to claim 29 wherein saidselection of a vacant address in the shared buffer memoryincludesmaintaining a linked list of vacant addresses; removing anaddress from said linked list when assigned for storage of a data cell;and adding an address to said linked list when the data cell stored atthe address has been transmitted from all selected ports for said datacell.
 31. The method according to claim 29 wherein said selection of avacant address in the shared buffer memory includesmaintaining a memorymap to indicate currently assigned exit ports for stored data cells; andusing parallel flow through logic in a content addressable memory todetermine a vacant address.
 32. The method according to claim 29 whereinthe header of said incoming data cell is examined and translated todetermine the output port or ports and the cell priority.
 33. The methodaccording to claim 32 for routing data cells according to virtual pathand circuit designations in the data cell wherein said translation is ona data compressed format according to the number of virtual paths andcircuits being serviced.
 34. The method according to claim 32 whereinthe header of said incoming data cell is translated while other datacells are being transfered to and from said shared memory on aword-by-word basis.
 35. The method according to claim 34 furtherincluding transmitting said data cell from one or more of said outputports when time is available, and translating the header of eachoutgoing data cell to change said header according to the outgoingtransmission link.
 36. The method according to claim 29 wherein saidstoring of said incoming data cell and said retrieving of said data cellis on a word-by-word interleaved basis.
 37. A method oftelecommunication priority switching of data cells between input portsand selected output ports, each data cell including a data cell priorityand each output port having a plurality of priority queues, includingthe steps of:receiving an incoming data cell via one of the input ports;using a shared buffer memory for storing said incoming data cellsreceived via the input ports while awaiting transmission via one or moreof the output ports; examining said incoming data cellto determine thedata cell priority, and to select one or more of the output ports forretransmission of the incoming data cell; selecting a vacant address insaid shared buffer memory for storing said incoming data cell;storingsaid incoming data cell to provide a stored data cell at said vacantaddress and storing said address in a priority queue selected accordingto said data cell priority at each of the one or more output portsselected for retransmission of said stored data cell; and retrievingsaid stored data cell in the shared memory for retransmission of saidstored data cell via each of the one or more selected output ports whensaid address is at the head of the highest occupied priority queue ateach of the one or more selected ports.
 38. The method according toclaim 37 wherein said selection of a vacant address in the shared buffermemory includesmaintaining a linked list of vacant addresses; removingan address from said linked list when assigned for storage of a datacell; and adding an address to said linked list when the data cellstored at the address has been transmitted from all selected ports forsaid data cell.
 39. The method according to claim 37 wherein saidselection of a vacant address in the shared buffer memoryincludesmaintaining a memory map to indicate currently assigned exitports for stored data cells; and using parallel flow through logic in acontent addressable memory to determine a vacant address.
 40. The methodaccording to claim 37 wherein the header of said incoming data cell isexamined and translated while other data cells are being transfered toand from said shared memory on a word-by-word basis.
 41. The methodaccording to claim 40 further including transmitting said data cell fromone or more of said output ports when time is available, and translatingthe header of each outgoing data cell to change said header according tothe outgoing transmission link.
 42. The method according to claim 37wherein said storing of said incoming data cell and said retrieving ofsaid data cell is on a word-by-word interleaved basis.
 43. A method oftelecommunication switching multi-word data cells between input portsand selected output ports, comprising the steps of:receiving an incomingdata cell at one of the input ports; using a shared buffer memory forstoring said incoming data cell received via the input ports whileawaiting retransmission via one or more of the output ports; examiningsaid incoming data cell to designate one or more of the output ports forretransmission of said incoming data cell; selecting a vacant address insaid shared buffer memory for storing said incoming data cell; storingsaid incoming data cell to provide a stored data cell at said vacantaddress and storing the address of said stored data cell at the one ormore output ports selected for retransmission of said cell; andretrieving said stored data cell at said address in said shared memorywhen time is available for retransmission of said stored data cell viaeach of the one or more selected output ports; the storing andretrieving of data cells to and from said shared buffer memory being onan interleaved word-by-word basis.
 44. The method according to claim 43wherein said selection of a vacant address in the shared buffer memoryincludesmaintaining a linked list of vacant addresses; removing anaddress from said linked list when assigned for storage of a data cell;and adding an address to said linked list when the data cell stored atthe address has been transmitted from all selected ports for said datacell.
 45. The method according to claim 43 wherein said selection of avacant address in the shared buffer memory includesmaintaining a memorymap to indicate currently assigned exit ports for stored data cells; andusing parallel flow through logic in a content addressable memory todetermine a vacant address.
 46. The method according to claim 43 whereinthe header of said incoming data cell is examined and translated todetermine the output port or ports and the cell priority.
 47. The methodaccording to claim 46 for routing data cells according to virtual pathand circuit designations in the data cell wherein said translation is ona data compressed format according to the number of virtual paths andcircuits being serviced.
 48. The method according to claim 43 whereinthe header of said incoming data cell is examined and translated whileother data cells are being transfered to and from said shared memory ona word-by-word basis.
 49. The method according to claim 48 furtherincluding transmitting said data cell from one or more of said outputports when time is available, and translating the header of eachoutgoing data cell to change said header according to the outgoingtransmission link.
 50. A method of telecommunication priority switchingof multi-word data cells between input ports and selected output ports,each output port having a plurality of priority queues and each of saiddata cells including a data cell priority, including the stepsof:receiving an incoming data cell via one the input ports; using ashared buffer memory for storing incoming data cells received via theinput ports while awaiting transmission via one or more of the outputports; examining the incoming data cellto determine the data cellpriority, and to select one or more of the output ports appropriate forretransmission of the cell; selecting a vacant address in said sharedbuffer memory for storing said incoming data cell; storing said incomingdata cell at said vacant address to provide a stored data cell andstoring said address in a priority queue selected according to said datacell priority at each of the one or more output ports selected forretransmission of said stored data cell; and retrieving said stored datacell at said address in the shared memory for retransmission of saidstored data cell via each of the one or more selected output ports whensaid address is at the head of the highest occupied priority queue atthe selected ports; the storing and retrieving of data cells to and fromsaid shared buffer memory being on an interleaved word-by-word basis.51. The method according to claim 50 wherein said selection of a vacantaddress in the shared buffer memory includesmaintaining a linked list ofvacant addresses; removing an address from said linked list whenassigned for storage of a data cell; and adding an address to saidlinked list when the data cell stored at the address has beentransmitted from all selected ports for said data cell.
 52. The methodaccording to claim 50 wherein said selection of a vacant address in theshared buffer memory includesmaintaining a memory map to indicatecurrently assigned exit ports for stored data cells; and using parallelflow through logic in a content addressable memory to determine a vacantaddress.
 53. The method according to claim 50 for routing data cellsaccording to virtual path and circuit designations in the data cellwherein said examination of the received data cell includes atranslation on a data compressed format according to the number ofvirtual paths and circuits being serviced.
 54. The method according toclaim 50 wherein the header of said incoming data cell is translatedwhile other data cells are being transfered to and from said sharedmemory on a word-by-word basis.
 55. The method according to claim 54further including transmitting said data cell from one or more of saidoutput ports when time is available, and translating the header of eachoutgoing data cell to change said header according to the outgoingtransmission link.